Ever considered SystemC ?

In recent years a lot of new C-based design languages have been developed. They all promise a smoother transition from a high level to a low level description of a hardware system. A disadvantage of these new languages is that a lot of simulation models of e.g. FPGA-cores are only available in standard languages like VHDL or Verilog. This makes it hard to develop a complete system with one of those new languages. However in a modular design approach this should not cause a problem. Here a distinction is made between application specific and hardware platform specific modules. It is possible to describe the application at a high level with e.g. SystemC and refine its modules with the same language, using simple models of the underlying hardware, until a level where translation to VHDL/Verilog is trivial. The platform specific modules can then be developed bottom up using the available VHDL/Verilog models of the used cores. In this paper the design of an IDWT is taken as a testcase. The design traject starts from a C-description and uses SystemC to arrive at a synthesizable level where an automatic translation to VHDL is done, which allows implementation on an FPGA. One can conclude that although tool support is only emerging recently for these new C-based languages their benefits can already be exploited when using the right language at the right place. Keywords— SystemC, inverse wavelet transformation, modular design, scalable wavelet video decoder, reconfigurable hardware.